On Thu, Oct 15, 2020 at 05:53:40PM +0300, Or Gerlitz wrote: > Hi, > > Earlier Intel processors (e.g E5-2650) support the more of classical > two stall events (for backend and frontend [1]) and then perf shows > the nice measure of stalled cycles per instruction - e.g here where we > have IPC of 0.91 and CSPI (see [2]) of 0.68:
Don't use it. It's misleading on a out-of-order CPU because you don't know if it's actually limiting anything. If you want useful bottleneck data use --topdown. -Andi
