Transitioning the enetc driver from phylib to phylink. Offloading the serdes configuration to the PCS_LYNX module is a mandatory part of this transition. Aiming for a cleaner, more maintainable design, and better code reuse. The first 2 patches are clean up prerequisites.
Tested on a p1028rdb board. v2: validate() explicitly rejects now all interface modes not supported by the driver instead of relying on the device tree to provide only supported interfaces, and dropped redundant activation of pcs_poll (addressing Ioana's findings) Claudiu Manoil (4): enetc: Clean up MAC and link configuration enetc: Clean up serdes configuration arm64: dts: fsl-ls1028a-rdb: Specify in-band mode for ENETC port 0 enetc: Migrate to PHYLINK and PCS_LYNX .../boot/dts/freescale/fsl-ls1028a-rdb.dts | 1 + drivers/net/ethernet/freescale/enetc/Kconfig | 5 +- drivers/net/ethernet/freescale/enetc/enetc.c | 53 ++- drivers/net/ethernet/freescale/enetc/enetc.h | 9 +- .../ethernet/freescale/enetc/enetc_ethtool.c | 26 +- .../net/ethernet/freescale/enetc/enetc_pf.c | 335 ++++++++++-------- .../net/ethernet/freescale/enetc/enetc_pf.h | 8 +- .../net/ethernet/freescale/enetc/enetc_qos.c | 9 +- 8 files changed, 243 insertions(+), 203 deletions(-) -- 2.17.1
