Annotate the EMDIO1 node and describe the 2 AQR107 PHYs found on the
LX2160ARDB board. Also, add the necessary phy-handles for DPMACs 3 and 4
to their associated PHY.

Signed-off-by: Ioana Ciornei <ioana.cior...@nxp.com>
---
Changes in v2:
 - none

 .../boot/dts/freescale/fsl-lx2160a-rdb.dts    | 32 +++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts 
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 54fe8cd3a711..7723ad5efd37 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -35,6 +35,18 @@ &crypto {
        status = "okay";
 };
 
+&dpmac3 {
+       phy-handle = <&aquantia_phy1>;
+       phy-connection-type = "usxgmii";
+       managed = "in-band-status";
+};
+
+&dpmac4 {
+       phy-handle = <&aquantia_phy2>;
+       phy-connection-type = "usxgmii";
+       managed = "in-band-status";
+};
+
 &dpmac17 {
        phy-handle = <&rgmii_phy1>;
        phy-connection-type = "rgmii-id";
@@ -61,6 +73,18 @@ rgmii_phy2: ethernet-phy@2 {
                reg = <0x2>;
                eee-broken-1000t;
        };
+
+       aquantia_phy1: ethernet-phy@4 {
+               /* AQR107 PHY */
+               compatible = "ethernet-phy-ieee802.3-c45";
+               reg = <0x4>;
+       };
+
+       aquantia_phy2: ethernet-phy@5 {
+               /* AQR107 PHY */
+               compatible = "ethernet-phy-ieee802.3-c45";
+               reg = <0x5>;
+       };
 };
 
 &esdhc0 {
@@ -156,6 +180,14 @@ rtc@51 {
        };
 };
 
+&pcs_mdio3 {
+       status = "okay";
+};
+
+&pcs_mdio4 {
+       status = "okay";
+};
+
 &sata0 {
        status = "okay";
 };
-- 
2.28.0

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