On 9/29/20 11:15 PM, Joakim Zhang wrote: > One issue was reported at a baremetal environment, which is used for > FPGA verification. "The first transfer will fail for extended ID > format(for both 2.0B and FD format), following frames can be transmitted > and received successfully for extended format, and standard format don't > have this issue. This issue occurred randomly with high possiblity, when > it occurs, the transmitter will detect a BIT1 error, the receiver a CRC > error. According to the spec, a non-correctable error may cause this > transfer failure." > > With FLEXCAN_QUIRK_DISABLE_MECR quirk, it supports correctable errors, > disable non-correctable errors interrupt and freeze mode. Platform has > ECC hardware support, but select this quirk, this issue may not come to > light. Initialize all FlexCAN memory before accessing them, at least it > can avoid non-correctable errors detected due to memory uninitialized. > The internal region can't be initialized when the hardware doesn't support > ECC. > > According to IMX8MPRM, Rev.C, 04/2020. There is a NOTE at the section > 11.8.3.13 Detection and correction of memory errors: > "All FlexCAN memory must be initialized before starting its operation in > order to have the parity bits in memory properly updated. CTRL2[WRMFRZ] > grants write access to all memory positions that require initialization, > ranging from 0x080 to 0xADF and from 0xF28 to 0xFFF when the CAN FD feature > is enabled. The RXMGMASK, RX14MASK, RX15MASK, and RXFGMASK registers need to > be initialized as well. MCR[RFEN] must not be set during memory > initialization." > > Memory range from 0x080 to 0xADF, there are reserved memory (unimplemented > by hardware, e.g. only configure 64 MBs), these memory can be initialized or > not. > In this patch, initialize all flexcan memory which includes reserved memory. > > In this patch, create FLEXCAN_QUIRK_SUPPORT_ECC for platforms which has ECC > feature. If you have a ECC platform in your hand, please select this > qurik to initialize all flexcan memory firstly, then you can select > FLEXCAN_QUIRK_DISABLE_MECR to only enable correctable errors. > > Signed-off-by: Joakim Zhang <qiangqing.zh...@nxp.com> > --- > ChangeLogs: > V1->V2: > * update commit messages, add a datasheet reference. > * initialize block memory instead of trivial memory. > * inilialize reserved memory. > V2->V3: > * add FLEXCAN_QUIRK_SUPPORT_ECC quirk. > * remove init_ram struct. > V3->V4: > * move register definition into flexcan_reg. > V4->V5: > * use offsetof instead of cast
looks good now. Should I try to get this into v5.10? Marc -- Pengutronix e.K. | Marc Kleine-Budde | Embedded Linux | https://www.pengutronix.de | Vertretung West/Dortmund | Phone: +49-231-2826-924 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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