[PATCH net-next 06/10] net: ipa: share field mask values for GSI global interrupt

[Alex Elder]

The GSI global interrupt is managed by three registers: enable;
status; and clear.  The three registers have same set of field bits
at the same locations.  Use a common set of field masks for all
three registers to avoid duplication.

Signed-off-by: Alex Elder <el...@linaro.org>
---
 drivers/net/ipa/gsi.c     |  4 ++--
 drivers/net/ipa/gsi_reg.h | 21 ++++++---------------
 2 files changed, 8 insertions(+), 17 deletions(-)

diff --git a/drivers/net/ipa/gsi.c b/drivers/net/ipa/gsi.c
index 745717477cad3..203d079c481c4 100644
--- a/drivers/net/ipa/gsi.c
+++ b/drivers/net/ipa/gsi.c
@@ -1074,8 +1074,8 @@ static void gsi_isr_glob_ee(struct gsi *gsi)
 
        val &= ~ERROR_INT_FMASK;
 
-       if (val & EN_GP_INT1_FMASK) {
-               val ^= EN_GP_INT1_FMASK;
+       if (val & GP_INT1_FMASK) {
+               val ^= GP_INT1_FMASK;
                gsi_isr_gp_int1(gsi);
        }
 
diff --git a/drivers/net/ipa/gsi_reg.h b/drivers/net/ipa/gsi_reg.h
index 598db57a68dfb..b789e0f866fa0 100644
--- a/drivers/net/ipa/gsi_reg.h
+++ b/drivers/net/ipa/gsi_reg.h
@@ -321,29 +321,20 @@
                        GSI_EE_N_CNTXT_GLOB_IRQ_STTS_OFFSET(GSI_EE_AP)
 #define GSI_EE_N_CNTXT_GLOB_IRQ_STTS_OFFSET(ee) \
                        (0x0001f100 + 0x4000 * (ee))
-#define ERROR_INT_FMASK                        GENMASK(0, 0)
-#define GP_INT1_FMASK                  GENMASK(1, 1)
-#define GP_INT2_FMASK                  GENMASK(2, 2)
-#define GP_INT3_FMASK                  GENMASK(3, 3)
-
 #define GSI_CNTXT_GLOB_IRQ_EN_OFFSET \
                        GSI_EE_N_CNTXT_GLOB_IRQ_EN_OFFSET(GSI_EE_AP)
 #define GSI_EE_N_CNTXT_GLOB_IRQ_EN_OFFSET(ee) \
                        (0x0001f108 + 0x4000 * (ee))
-#define EN_ERROR_INT_FMASK             GENMASK(0, 0)
-#define EN_GP_INT1_FMASK               GENMASK(1, 1)
-#define EN_GP_INT2_FMASK               GENMASK(2, 2)
-#define EN_GP_INT3_FMASK               GENMASK(3, 3)
-#define GSI_CNTXT_GLOB_IRQ_ALL         GENMASK(3, 0)
-
 #define GSI_CNTXT_GLOB_IRQ_CLR_OFFSET \
                        GSI_EE_N_CNTXT_GLOB_IRQ_CLR_OFFSET(GSI_EE_AP)
 #define GSI_EE_N_CNTXT_GLOB_IRQ_CLR_OFFSET(ee) \
                        (0x0001f110 + 0x4000 * (ee))
-#define CLR_ERROR_INT_FMASK            GENMASK(0, 0)
-#define CLR_GP_INT1_FMASK              GENMASK(1, 1)
-#define CLR_GP_INT2_FMASK              GENMASK(2, 2)
-#define CLR_GP_INT3_FMASK              GENMASK(3, 3)
+/* The masks below are used for the general IRQ STTS, EN, and CLR registers */
+#define ERROR_INT_FMASK                        GENMASK(0, 0)
+#define GP_INT1_FMASK                  GENMASK(1, 1)
+#define GP_INT2_FMASK                  GENMASK(2, 2)
+#define GP_INT3_FMASK                  GENMASK(3, 3)
+#define GSI_CNTXT_GLOB_IRQ_ALL         GENMASK(3, 0)
 
 #define GSI_CNTXT_GSI_IRQ_STTS_OFFSET \
                        GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(GSI_EE_AP)
-- 
2.20.1