Hi Dan,

I love your patch! Perhaps something to improve:

[auto build test WARNING on net-next/master]

url:    
https://github.com/0day-ci/linux/commits/Dan-Murphy/DP83869-Feature-additions/20200903-043618
base:   https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git 
dc1a9bf2c8169d9f607502162af1858a73a18cb8
config: i386-randconfig-m021-20200902 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <l...@intel.com>

smatch warnings:
drivers/net/phy/dp83869.c:669 dp83869_config_init() warn: inconsistent indenting

# 
https://github.com/0day-ci/linux/commit/307ae0a0e8406ceadb72d448df96322bbd23aa92
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review 
Dan-Murphy/DP83869-Feature-additions/20200903-043618
git checkout 307ae0a0e8406ceadb72d448df96322bbd23aa92
vim +669 drivers/net/phy/dp83869.c

   662  
   663  static int dp83869_config_init(struct phy_device *phydev)
   664  {
   665          struct dp83869_private *dp83869 = phydev->priv;
   666          int ret, val;
   667  
   668         /* Force speed optimization for the PHY even if it strapped */
 > 669         ret = phy_modify(phydev, DP83869_CFG2, DP83869_DOWNSHIFT_EN,
   670                          DP83869_DOWNSHIFT_EN);
   671         if (ret)
   672                 return ret;
   673  
   674          ret = dp83869_configure_mode(phydev, dp83869);
   675          if (ret)
   676                  return ret;
   677  
   678          /* Enable Interrupt output INT_OE in CFG4 register */
   679          if (phy_interrupt_is_valid(phydev)) {
   680                  val = phy_read(phydev, DP83869_CFG4);
   681                  val |= DP83869_INT_OE;
   682                  phy_write(phydev, DP83869_CFG4, val);
   683          }
   684  
   685          if (dp83869->port_mirroring != DP83869_PORT_MIRRORING_KEEP)
   686                  dp83869_config_port_mirroring(phydev);
   687  
   688          /* Clock output selection if muxing property is set */
   689          if (dp83869->clk_output_sel != DP83869_CLK_O_SEL_REF_CLK)
   690                  ret = phy_modify_mmd(phydev,
   691                                       DP83869_DEVADDR, 
DP83869_IO_MUX_CFG,
   692                                       DP83869_IO_MUX_CFG_CLK_O_SEL_MASK,
   693                                       dp83869->clk_output_sel <<
   694                                       
DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT);
   695  
   696          if (phy_interface_is_rgmii(phydev)) {
   697                  ret = phy_write_mmd(phydev, DP83869_DEVADDR, 
DP83869_RGMIIDCTL,
   698                                      dp83869->rx_int_delay |
   699                          dp83869->tx_int_delay << 
DP83869_RGMII_CLK_DELAY_SHIFT);
   700                  if (ret)
   701                          return ret;
   702  
   703                  val = phy_read_mmd(phydev, DP83869_DEVADDR, 
DP83869_RGMIICTL);
   704                  val &= ~(DP83869_RGMII_TX_CLK_DELAY_EN |
   705                           DP83869_RGMII_RX_CLK_DELAY_EN);
   706  
   707                  if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
   708                          val |= (DP83869_RGMII_TX_CLK_DELAY_EN |
   709                                  DP83869_RGMII_RX_CLK_DELAY_EN);
   710  
   711                  if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
   712                          val |= DP83869_RGMII_TX_CLK_DELAY_EN;
   713  
   714                  if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
   715                          val |= DP83869_RGMII_RX_CLK_DELAY_EN;
   716  
   717                  ret = phy_write_mmd(phydev, DP83869_DEVADDR, 
DP83869_RGMIICTL,
   718                                      val);
   719          }
   720  
   721          return ret;
   722  }
   723  

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org

Attachment: .config.gz
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