Hi Andrew.
W dniu 2020-08-29 o 00:28, Andrew Lunn pisze:
Hi Adam
If kernel has to bring up two Ethernet interfaces, the processor has two
peripherals with functionality of MACs (in i.MX6ULL these are Fast Ethernet
Controllers, FECs), but uses a shared MDIO bus, then the kernel first probes
one MAC, enables clock for its PHY, probes MDIO bus tryng to discover _all_
PHYs, and then probes the second MAC, and enables clock for its PHY. The
result is that the second PHY is still inactive during PHY discovery. Thus,
one Ethernet interface is not functional.
What clock are you talking about? Do you have the FEC feeding a 50MHz
clock to the PHY? Each FEC providing its own clock to its own PHY? And
are you saying a PHY without its reference clock does not respond to
MDIO reads and hence the second PHY does not probe because it has no
reference clock?
Andrew
Yes, exactly. In my case the PHYs are LAN8720A, and it works this way.
Maybe this problem is PHY-related.
I also think that my proposition allows to make device tree look better
and be less confusing, as a side-effect.
Best regards,
Adam
