[PATCH v2] net: dp83869: Fix RGMII internal delay configuration

[Daniel Gorsulowski]

The RGMII control register at 0x32 indicates the states for the bits
RGMII_TX_CLK_DELAY and RGMII_RX_CLK_DELAY as follows:

  RGMII Transmit/Receive Clock Delay
    0x0 = RGMII transmit clock is shifted with respect to transmit/receive data.
    0x1 = RGMII transmit clock is aligned with respect to transmit/receive data.

This commit fixes the inversed behavior of these bits

Fixes: 736b25afe284 ("net: dp83869: Add RGMII internal delay configuration")
Signed-off-by: Daniel Gorsulowski <daniel.gorsulow...@esd.eu>
---
v2: fixed indentation and commit style

 drivers/net/phy/dp83869.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c
index 58103152c601..6b98d74b5102 100644
--- a/drivers/net/phy/dp83869.c
+++ b/drivers/net/phy/dp83869.c
@@ -427,18 +427,18 @@ static int dp83869_config_init(struct phy_device *phydev)
                        return ret;
 
                val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL);
-               val &= ~(DP83869_RGMII_TX_CLK_DELAY_EN |
-                        DP83869_RGMII_RX_CLK_DELAY_EN);
+               val |= (DP83869_RGMII_TX_CLK_DELAY_EN |
+                       DP83869_RGMII_RX_CLK_DELAY_EN);
 
                if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
-                       val |= (DP83869_RGMII_TX_CLK_DELAY_EN |
-                               DP83869_RGMII_RX_CLK_DELAY_EN);
+                       val &= ~(DP83869_RGMII_TX_CLK_DELAY_EN |
+                                DP83869_RGMII_RX_CLK_DELAY_EN);
 
                if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
-                       val |= DP83869_RGMII_TX_CLK_DELAY_EN;
+                       val &= ~DP83869_RGMII_TX_CLK_DELAY_EN;
 
                if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
-                       val |= DP83869_RGMII_RX_CLK_DELAY_EN;
+                       val &= ~DP83869_RGMII_RX_CLK_DELAY_EN;
 
                ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL,
                                    val);
-- 
2.25.1