From: <akiy...@amazon.com> Date: Thu, 16 Jul 2020 21:10:03 +0300 > To the best of my knowledge this assumption holds for ARM64 and x86_64 > architecture which use a MESI like cache coherency model.
Use the well defined kernel memory model correctly please. This is no place for architectural assumptions. The memory model of the kernel defines the rules, and in what locations various memory barriers are required for correct operation. Thank you.
