Add dt nodes with serdes, lanes, mdio generic description for supported
platform: ls1046. This is a prerequisite to enable backplane on device
tree for these platforms.
Signed-off-by: Florinel Iordache <florinel.iorda...@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 33 +++++++++++++++++++++-
.../boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi | 5 ++--
.../boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi | 5 ++--
3 files changed, 38 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index d4c1da3..c7d845f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -3,7 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
+ * Copyright 2018, 2020 NXP
*
* Mingkai Hu <mingkai...@nxp.com>
*/
@@ -735,6 +735,37 @@
status = "disabled";
};
+ serdes1: serdes@1ea0000 {
+ compatible = "serdes-10g";
+ reg = <0x0 0x1ea0000 0 0x00002000>;
+ reg-names = "serdes", "serdes-10g";
+ big-endian;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x1ea0000 0x00002000>;
+ lane_a: lane@800 {
+ compatible = "lane-10g";
+ reg = <0x800 0x40>;
+ reg-names = "lane", "serdes-lane";
+ };
+ lane_b: lane@840 {
+ compatible = "lane-10g";
+ reg = <0x840 0x40>;
+ reg-names = "lane", "serdes-lane";
+ };
+ lane_c: lane@880 {
+ compatible = "lane-10g";
+ reg = <0x880 0x40>;
+ reg-names = "lane", "serdes-lane";
+ };
+ lane_d: lane@8c0 {
+ compatible = "lane-10g";
+ reg = <0x8c0 0x40>;
+ reg-names = "lane", "serdes-lane";
+ };
+ };
+
pcie_ep@3600000 {
compatible = "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep";
reg = <0x00 0x03600000 0x0 0x00100000
diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi
b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi
index dbd2fc3..d6191f1 100644
--- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi
+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi
@@ -3,6 +3,7 @@
* QorIQ FMan v3 10g port #0 device tree
*
* Copyright 2012-2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
*
*/
@@ -21,7 +22,7 @@ fman@1a00000 {
fsl,fman-10g-port;
};
- ethernet@f0000 {
+ mac9: ethernet@f0000 {
cell-index = <0x8>;
compatible = "fsl,fman-memac";
reg = <0xf0000 0x1000>;
@@ -29,7 +30,7 @@ fman@1a00000 {
pcsphy-handle = <&pcsphy6>;
};
- mdio@f1000 {
+ mdio9: mdio@f1000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi
b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi
index 6fc5d25..1f6f28f 100644
--- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi
+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi
@@ -3,6 +3,7 @@
* QorIQ FMan v3 10g port #1 device tree
*
* Copyright 2012-2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
*
*/
@@ -21,7 +22,7 @@ fman@1a00000 {
fsl,fman-10g-port;
};
- ethernet@f2000 {
+ mac10: ethernet@f2000 {
cell-index = <0x9>;
compatible = "fsl,fman-memac";
reg = <0xf2000 0x1000>;
@@ -29,7 +30,7 @@ fman@1a00000 {
pcsphy-handle = <&pcsphy7>;
};
- mdio@f3000 {
+ mdio10: mdio@f3000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
--
1.9.1
