Add the internal delay values into the header and update the binding
with the internal delay properties.
Signed-off-by: Dan Murphy <dmur...@ti.com>
---
.../devicetree/bindings/net/ti,dp83869.yaml | 16 ++++++++++++++++
include/dt-bindings/net/ti-dp83869.h | 18 ++++++++++++++++++
2 files changed, 34 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/ti,dp83869.yaml
b/Documentation/devicetree/bindings/net/ti,dp83869.yaml
index 5b69ef03bbf7..344015ab9081 100644
--- a/Documentation/devicetree/bindings/net/ti,dp83869.yaml
+++ b/Documentation/devicetree/bindings/net/ti,dp83869.yaml
@@ -64,6 +64,20 @@ properties:
Operational mode for the PHY. If this is not set then the operational
mode is set by the straps. see dt-bindings/net/ti-dp83869.h for values
+ ti,rx-internal-delay:
+ $ref: /schemas/types.yaml#definitions/uint32
+ description: |
+ RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83869.h
+ for applicable values. Required only if interface type is
+ PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_RXID.
+
+ ti,tx-internal-delay:
+ $ref: /schemas/types.yaml#definitions/uint32
+ description: |
+ RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83869.h
+ for applicable values. Required only if interface type is
+ PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_TXID.
+
required:
- reg
@@ -80,5 +94,7 @@ examples:
ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>;
ti,max-output-impedance = "true";
ti,clk-output-sel = <DP83869_CLK_O_SEL_CHN_A_RCLK>;
+ ti,rx-internal-delay = <DP83869_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83869_RGMIIDCTL_2_75_NS>;
};
};
diff --git a/include/dt-bindings/net/ti-dp83869.h
b/include/dt-bindings/net/ti-dp83869.h
index 218b1a64e975..77d104a40f1f 100644
--- a/include/dt-bindings/net/ti-dp83869.h
+++ b/include/dt-bindings/net/ti-dp83869.h
@@ -16,6 +16,24 @@
#define DP83869_PHYCR_FIFO_DEPTH_6_B_NIB 0x02
#define DP83869_PHYCR_FIFO_DEPTH_8_B_NIB 0x03
+/* RGMIIDCTL internal delay for rx and tx */
+#define DP83869_RGMIIDCTL_250_PS 0x0
+#define DP83869_RGMIIDCTL_500_PS 0x1
+#define DP83869_RGMIIDCTL_750_PS 0x2
+#define DP83869_RGMIIDCTL_1_NS 0x3
+#define DP83869_RGMIIDCTL_1_25_NS 0x4
+#define DP83869_RGMIIDCTL_1_50_NS 0x5
+#define DP83869_RGMIIDCTL_1_75_NS 0x6
+#define DP83869_RGMIIDCTL_2_00_NS 0x7
+#define DP83869_RGMIIDCTL_2_25_NS 0x8
+#define DP83869_RGMIIDCTL_2_50_NS 0x9
+#define DP83869_RGMIIDCTL_2_75_NS 0xa
+#define DP83869_RGMIIDCTL_3_00_NS 0xb
+#define DP83869_RGMIIDCTL_3_25_NS 0xc
+#define DP83869_RGMIIDCTL_3_50_NS 0xd
+#define DP83869_RGMIIDCTL_3_75_NS 0xe
+#define DP83869_RGMIIDCTL_4_00_NS 0xf
+
/* IO_MUX_CFG - Clock output selection */
#define DP83869_CLK_O_SEL_CHN_A_RCLK 0x0
#define DP83869_CLK_O_SEL_CHN_B_RCLK 0x1
--
2.26.2
