[PATCH net-next 4/4] net: dp83869: Add RGMII internal delay configuration

[Dan Murphy]

Add RGMII internal delay configuration for Rx and Tx.

Signed-off-by: Dan Murphy <dmur...@ti.com>
---
 drivers/net/phy/dp83869.c | 84 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 84 insertions(+)

diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c
index 64fa2d911074..7d0b11220e47 100644
--- a/drivers/net/phy/dp83869.c
+++ b/drivers/net/phy/dp83869.c
@@ -99,6 +99,14 @@
 #define DP83869_OP_MODE_MII                    BIT(5)
 #define DP83869_SGMII_RGMII_BRIDGE             BIT(6)
 
+/* RGMIIDCTL bits */
+#define DP83869_RGMII_TX_CLK_DELAY_MAX         0xf
+#define DP83869_RGMII_TX_CLK_DELAY_SHIFT       4
+#define DP83869_RGMII_TX_CLK_DELAY_INV (DP83869_RGMII_TX_CLK_DELAY_MAX + 1)
+#define DP83869_RGMII_RX_CLK_DELAY_MAX         0xf
+#define DP83869_RGMII_RX_CLK_DELAY_SHIFT       0
+#define DP83869_RGMII_RX_CLK_DELAY_INV (DP83869_RGMII_RX_CLK_DELAY_MAX + 1)
+
 enum {
        DP83869_PORT_MIRRORING_KEEP,
        DP83869_PORT_MIRRORING_EN,
@@ -108,6 +116,8 @@ enum {
 struct dp83869_private {
        int tx_fifo_depth;
        int rx_fifo_depth;
+       u32 rx_id_delay;
+       u32 tx_id_delay;
        int io_impedance;
        int port_mirroring;
        bool rxctrl_strap_quirk;
@@ -232,6 +242,26 @@ static int dp83869_of_init(struct phy_device *phydev)
                                 &dp83869->tx_fifo_depth))
                dp83869->tx_fifo_depth = DP83869_PHYCR_FIFO_DEPTH_4_B_NIB;
 
+       dp83869->rx_id_delay = DP83869_RGMII_RX_CLK_DELAY_INV;
+       ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
+                                  &dp83869->rx_id_delay);
+       if (!ret && dp83869->rx_id_delay > DP83869_RGMII_RX_CLK_DELAY_MAX) {
+               phydev_err(phydev,
+                          "ti,rx-internal-delay value of %u out of range\n",
+                          dp83869->rx_id_delay);
+               return -EINVAL;
+       }
+
+       dp83869->tx_id_delay = DP83869_RGMII_TX_CLK_DELAY_INV;
+       ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
+                                  &dp83869->tx_id_delay);
+       if (!ret && dp83869->tx_id_delay > DP83869_RGMII_TX_CLK_DELAY_MAX) {
+               phydev_err(phydev,
+                          "ti,tx-internal-delay value of %u out of range\n",
+                          dp83869->tx_id_delay);
+               return -EINVAL;
+       }
+
        return ret;
 }
 #else
@@ -270,6 +300,29 @@ static int dp83869_configure_rgmii(struct phy_device 
*phydev,
        return ret;
 }
 
+static int dp83869_verify_rgmii_cfg(struct phy_device *phydev)
+{
+       struct dp83869_private *dp83869 = phydev->priv;
+
+       /* RX delay *must* be specified if internal delay of RX is used. */
+       if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+            phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) &&
+            dp83869->rx_id_delay == DP83869_RGMII_RX_CLK_DELAY_INV) {
+               phydev_err(phydev, "ti,rx-internal-delay must be specified\n");
+               return -EINVAL;
+       }
+
+       /* TX delay *must* be specified if internal delay of TX is used. */
+       if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+            phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) &&
+            dp83869->tx_id_delay == DP83869_RGMII_TX_CLK_DELAY_INV) {
+               phydev_err(phydev, "ti,tx-internal-delay must be specified\n");
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
 static int dp83869_configure_mode(struct phy_device *phydev,
                                  struct dp83869_private *dp83869)
 {
@@ -371,6 +424,11 @@ static int dp83869_config_init(struct phy_device *phydev)
 {
        struct dp83869_private *dp83869 = phydev->priv;
        int ret, val;
+       u16 delay;
+
+       ret = dp83869_verify_rgmii_cfg(phydev);
+       if (ret)
+               return ret;
 
        ret = dp83869_configure_mode(phydev, dp83869);
        if (ret)
@@ -394,6 +452,32 @@ static int dp83869_config_init(struct phy_device *phydev)
                                     dp83869->clk_output_sel <<
                                     DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT);
 
+       if (phy_interface_is_rgmii(phydev)) {
+               val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL);
+
+               val &= ~(DP83869_RGMII_TX_CLK_DELAY_EN | 
DP83869_RGMII_RX_CLK_DELAY_EN);
+               if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
+                       val |= (DP83869_RGMII_TX_CLK_DELAY_EN | 
DP83869_RGMII_RX_CLK_DELAY_EN);
+
+               if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
+                       val |= DP83869_RGMII_TX_CLK_DELAY_EN;
+
+               if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
+                       val |= DP83869_RGMII_RX_CLK_DELAY_EN;
+
+               phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL, val);
+
+               delay = 0;
+               if (dp83869->rx_id_delay != DP83869_RGMII_RX_CLK_DELAY_INV)
+                       delay |= dp83869->rx_id_delay;
+               if (dp83869->tx_id_delay != DP83869_RGMII_TX_CLK_DELAY_INV)
+                       delay |= dp83869->tx_id_delay <<
+                                DP83869_RGMII_TX_CLK_DELAY_SHIFT;
+
+               phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIIDCTL,
+                             delay);
+       }
+
        return ret;
 }
 
-- 
2.26.2