Hi Andrew,
On Sun, May 17 2020, Andrew Lunn wrote:
>> > I don't think this should be done at mdiobus level; I think this is a
>> > layering violation. It needs to happen at the PHY level because the
>> > indirect C45 access via C22 registers is specific to PHYs.
>> >
>> > It also needs to check in the general case that the PHY does indeed
>> > support the C22 register set - not all C45 PHYs do.
>> >
>> > So, I think we want this fallback to be conditional on:
>> >
>> > - are we probing for the PHY, trying to read its IDs and
>> > devices-in-package registers - if yes, allow fallback.
>> > - does the C45 PHY support the C22 register set - if yes, allow
>> > fallback.
>>
>> I'll take a look. Thanks.
>
> Another option to consider is a third compatible string. We have
> compatibles for C22, C45. Add another one for C45 over C22, and have
> the core support it as the third access method next to C22 and C45.
>
> We already rely on the DT author getting C22 vs C45 correct for the
> hardware. Is it too much to ask they get it write when there are three
> options?
Networking hardware DT configuration is confusing enough already. Since
we can determine indirect C45 access automatically, I think we should do
that.
> As to your particular hardware, if i remember correctly, some of the
> Marvell SoCs have mdio and xmdio bus masters. The mdio bus can only do
> C22, and the xmdio can only do C45. Have the hardware engineers put
> the PHY on the wrong bus?
The Armada 385 has only C22 MDIO. Other Armada SoCs have both MDIO and
XMDIO.
baruch
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