> Here is my device tree
>
> mdio {
> #address-cells = <1>;
> #size-cells = <0>;
>
> switch0: switch0@0 {
> compatible = "marvell,mv88e6085";
> reg = <0x0>;
> pinctrl-0 = <&lcd_d06_pins>;
> reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
>
> dsa,member = <0 0>;
>
> ports {
> #address-cells = <1>;
> #size-cells = <0>;
>
> port@0 {
> /* Changed reg to 0xc too, same error message */
> reg = <0x0>;
> label = "Serdes0";
> phy-handle = <&switch0phy0>;
> };
>
> port@1 {
> /* Changed reg to 0xd too, same error message */
> reg = <0x1>;
> label = "Serdes1";
> phy-handle = <&switch0phy1>;
> };
>
> port@2 {
> reg = <0x2>;
> label = "lan1";
> phy-handle = <&switch0phy2>;
> };
>
> port@3 {
> reg = <0x3>;
> label = "lan2";
> phy-handle = <&switch0phy3>;
> };
>
> port@4 {
> reg = <0x4>;
> label = "lan3";
> phy-handle = <&switch0phy4>;
> };
You don't need to list phy-handle for the internal PHYs. It should
just find them.
> mdio {
> #address-cells = <1>;
> #size-cells = <0>;
> switch0phy0: switch0phy0@0 {
> /* Changed reg to 0 too, same error message */
> reg = <0xc>;
> };
> switch0phy1: switch0phy1@1 {
> /* Changed reg to 1 too, same error message */
> reg = <0xd>;
> };
> switch0phy3: switch0phy3@3 {
> reg = <0x3>;
> };
> switch0phy4: switch0phy4@4 {
> reg = <0x4>;
> };
> };
>
> mdio1 {
> compatible = "marvell,mv88e6xxx-mdio-external";
> #address-cells = <1>;
> #size-cells = <0>;
>
> switch0phy2: switch0phy2@2 {
> reg = <0x2>;
> };
> switch0phy6: switch0phy6@6 {
> reg = <0x6>;
> };
> };
I doubt this second mdio bus is correct. The 6390 uses that, but i
don't think any other family does. The older generations have one MDIO
bus for both internal and external PHYs.
One other idea. Take a look at the data sheet. Can the MDIO pins also
be used for GPIO? Do they default to GPIO or MDIO? For the 6390 they
default to GPIO and there is code to reconfigure them for MDIO.
Andrew
