On Wed, 22 May 2019 at 20:13, Y Song <ys114...@gmail.com> wrote: > > On Wed, May 22, 2019 at 2:25 AM Björn Töpel <bjorn.to...@gmail.com> wrote: > > > > Add three tests to test_verifier/basic_instr that make sure that the > > high 32-bits of the destination register is cleared after an ALU32 > > and/or/xor. > > > > Signed-off-by: Björn Töpel <bjorn.to...@gmail.com> > > I think the patch intends for bpf-next, right? The patch itself looks > good to me. > Acked-by: Yonghong Song <y...@fb.com> >
Thank you. Actually, it was intended for the bpf tree, as a test follow up for this [1] fix. Cheers, Björn [1] https://lore.kernel.org/bpf/caj+hfnifkxkz8df7glbuqwa6+t6awrrrk6ow6m1nayetjd+...@mail.gmail.com/ > > --- > > .../selftests/bpf/verifier/basic_instr.c | 39 +++++++++++++++++++ > > 1 file changed, 39 insertions(+) > > > > diff --git a/tools/testing/selftests/bpf/verifier/basic_instr.c > > b/tools/testing/selftests/bpf/verifier/basic_instr.c > > index ed91a7b9a456..4d844089938e 100644 > > --- a/tools/testing/selftests/bpf/verifier/basic_instr.c > > +++ b/tools/testing/selftests/bpf/verifier/basic_instr.c > > @@ -132,3 +132,42 @@ > > .prog_type = BPF_PROG_TYPE_SCHED_CLS, > > .result = ACCEPT, > > }, > > +{ > > + "and32 reg zero extend check", > > + .insns = { > > + BPF_MOV64_IMM(BPF_REG_0, -1), > > + BPF_MOV64_IMM(BPF_REG_2, -2), > > + BPF_ALU32_REG(BPF_AND, BPF_REG_0, BPF_REG_2), > > + BPF_ALU64_IMM(BPF_RSH, BPF_REG_0, 32), > > + BPF_EXIT_INSN(), > > + }, > > + .prog_type = BPF_PROG_TYPE_SCHED_CLS, > > + .result = ACCEPT, > > + .retval = 0, > > +}, > > +{ > > + "or32 reg zero extend check", > > + .insns = { > > + BPF_MOV64_IMM(BPF_REG_0, -1), > > + BPF_MOV64_IMM(BPF_REG_2, -2), > > + BPF_ALU32_REG(BPF_OR, BPF_REG_0, BPF_REG_2), > > + BPF_ALU64_IMM(BPF_RSH, BPF_REG_0, 32), > > + BPF_EXIT_INSN(), > > + }, > > + .prog_type = BPF_PROG_TYPE_SCHED_CLS, > > + .result = ACCEPT, > > + .retval = 0, > > +}, > > +{ > > + "xor32 reg zero extend check", > > + .insns = { > > + BPF_MOV64_IMM(BPF_REG_0, -1), > > + BPF_MOV64_IMM(BPF_REG_2, 0), > > + BPF_ALU32_REG(BPF_XOR, BPF_REG_0, BPF_REG_2), > > + BPF_ALU64_IMM(BPF_RSH, BPF_REG_0, 32), > > + BPF_EXIT_INSN(), > > + }, > > + .prog_type = BPF_PROG_TYPE_SCHED_CLS, > > + .result = ACCEPT, > > + .retval = 0, > > +}, > > -- > > 2.20.1 > >
