On 04.03.2019 15:48, S-k, Shyam-sundar wrote: > Hi Heiner, > > We noticed that, the recent changes for CL45 in net-next tree causing > regression on AMD platforms. The following is the commit: > > 3ce2a02 net: phy: marvell10g: check for newly set aneg > > Now, I see that, this code is moved to phy-c45.c with newer commit > > 1af9f16 net: phy: add genphy_c45_check_and_restart_aneg > > With this change, the link never comes up. Can you please a re-look once > before it enters mainline? > > Thanks, > > Shyam > Hi Shyam,
thanks for the report. However the description quite vague, therefore I'd appreciate the following details: - The mentioned patch affects Marvell 10G PHY's only. Could you please provide: - exact PHY model you're using - interface mode you're using - link speed you expect and advertised speeds from both sides - Some details regarding "AMD platform" would be helpful. What kind of board is it? - There's a known issue in genphy_c45_an_config_aneg(), however I'm not sure whether it could be related to your issue. Could you please test the following patch whether it fixes the issue for you? https://patchwork.ozlabs.org/patch/1051291/ Heiner
