Please ignore this one - subject line is not correct. Thanks. On Sat, Feb 09, 2019 at 04:06:13PM +0000, Russell King wrote: > When mvpp2 configures the flow control modes in mvpp2_xlg_config() for > 10G mode, it only ever set the flow control enable bits. There is no > mechanism to clear these bits, which means that userspace is unable to > use standard APIs to disable flow control (the only way is to poke the > register directly.) > > Fix the missing bit clearance to allow flow control to be disabled. > This means that, by default, as there is no negotiation in 10G modes > with mvpp2, flow control is now disabled rather than being rx-only. > > Signed-off-by: Russell King <rmk+ker...@armlinux.org.uk> > --- > drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c > b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c > index b63fac6ee2e6..199e6f17ee1b 100644 > --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c > +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c > @@ -4532,8 +4532,13 @@ static void mvpp2_xlg_config(struct mvpp2_port *port, > unsigned int mode, > > if (state->pause & MLO_PAUSE_TX) > ctrl0 |= MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN; > + else > + ctrl0 &= ~MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN; > + > if (state->pause & MLO_PAUSE_RX) > ctrl0 |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN; > + else > + ctrl0 &= ~MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN; > > ctrl4 &= ~MVPP22_XLG_CTRL4_MACMODSELECT_GMAC; > ctrl4 |= MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC | > -- > 2.7.4 > >
-- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTC broadband for 0.8mile line in suburbia: sync at 12.1Mbps down 622kbps up According to speedtest.net: 11.9Mbps down 500kbps up
