Hello Russell, On Mon, 21 Jan 2019 13:00:30 +0000 Russell King - ARM Linux admin <li...@armlinux.org.uk> wrote:
>On Mon, Jan 21, 2019 at 01:29:45PM +0100, Maxime Chevallier wrote: >> Hello Russell, >> >> On Mon, 21 Jan 2019 10:52:06 +0000 >> Russell King - ARM Linux admin <li...@armlinux.org.uk> wrote: >> >It's entirely possible that the 3310 switches to different hardware >> >blocks for 2.5G and 5G speeds, and reading _just_ the 1.4 register >> >is not sufficient. >> >> I agree with you but in that particular case, I think we are reading >> from the correct device. The datasheet itself says that we should be >> reading 1.4 and 1.11 as we expect, with 2.5G/5G support being set (these >> registers are read-only, and the datasheet's values aren't what we >> actually read). > >No, you missed what I was saying. > >The 88x3310 is a hybrid device. It contains multiple instances of >each individual device at different offsets in each MMD address space. Ah I see, I indeed thought you refered to the MMDs. [...] >The exception seems to be the PMA/PMD MMD which I've only discovered >a single instance. Yes there only seems to be one. There are some other registers in the 1.0xCxxx range, but those who are documented don't help a lot with determing wether or not these modes are supported. I wonder if these values are correctly reported in newer PHY firmware revisions. I've checked other PCS instances, but it seems the one at 3.0x0xxx is the one used in 2.5/5GBASET. I've tested with other PHYs from this family, it looks like they are derivatives of the 33x0 design, with the addition/removal of internal IPs. Since the 2110 returns the correct values and has a similar design, with the PMA returning the correct abilities, I think we are reading from the correct instance. Thanks, Maxime -- Maxime Chevallier, Bootlin Embedded Linux and kernel engineering https://bootlin.com
