On Wed, Jan 16, 2019 at 06:37:53PM +0000, Fabrizio Castro wrote: > According to the latest information, clkp2 is available on RZ/G2. > Modify CAN0 and CAN1 nodes accordingly. > > Signed-off-by: Fabrizio Castro <fabrizio.cas...@bp.renesas.com> > Reviewed-by: Chris Paterson <chris.paters...@renesas.com>
Taking your word for the motivation for this change, this patch seems fine to me but I would like to wait for review from others. Reviewed-by: Simon Horman <horms+rene...@verge.net.au> > --- > arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 12 ++++++++---- > 1 file changed, 8 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi > b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi > index 3970aaf..326ab3a 100644 > --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi > @@ -809,8 +809,10 @@ > "renesas,rcar-gen3-can"; > reg = <0 0xe6c30000 0 0x1000>; > interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&cpg CPG_MOD 916>, <&can_clk>; > - clock-names = "clkp1", "can_clk"; > + clocks = <&cpg CPG_MOD 916>, > + <&cpg CPG_CORE R8A774C0_CLK_CANFD>, > + <&can_clk>; > + clock-names = "clkp1", "clkp2", "can_clk"; > power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; > resets = <&cpg 916>; > status = "disabled"; > @@ -821,8 +823,10 @@ > "renesas,rcar-gen3-can"; > reg = <0 0xe6c38000 0 0x1000>; > interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&cpg CPG_MOD 915>, <&can_clk>; > - clock-names = "clkp1", "can_clk"; > + clocks = <&cpg CPG_MOD 915>, > + <&cpg CPG_CORE R8A774C0_CLK_CANFD>, > + <&can_clk>; > + clock-names = "clkp1", "clkp2", "can_clk"; > power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; > resets = <&cpg 915>; > status = "disabled"; > -- > 2.7.4 >
