On Sun, Dec 30, 2018 at 09:25:53AM +0100, Klaus Kudielka wrote:
> Hello,
Hi Klaus
Thanks for reposting on the correct list.
> Apart from the 88E1514 PHY specified for eth2, the device also
> features an SFP cage, which uses the same SGMII of the Armada
> 385 SoC (a 2:1 multiplexer is driven by the MOD_DEF0 signal).
Some of the Marvell Ethernet switches have a similar setup. Some ports
have both an internal PHY and a SERDES port which can be connected to
an SFP cage. Whichever gets link first is connected to the MAC. I can
also imagine a slightly different setup to what you have, the MUX is
controlled via a GPIO, not MOD_DEF0, so again, you want both active
until one gets link, although SFP LOS is not very reliable for this.
So we need a generic solution to this. In your case, the PHY should be
configured down when the SFP is present, but then made active when the
SFP is unplugged. For the Marvell switch, we need both SFP and PHY
active until one gets a link, and then the other configured down. So
it sounds like we need some board specific code involved to implement
the board specific parts.
Andrew
