[PATCH net-next 1/2] r8169: simplify RTL8169 PHY initialization

[Heiner Kallweit]

PCI_LATENCY_TIMER is ignored on PCIe, therefore we have to do this
for the PCI chips (version <= 06) only. Also we can move setting
PCI_CACHE_LINE_SIZE.

Signed-off-by: Heiner Kallweit <hkallwe...@gmail.com>
---
 drivers/net/ethernet/realtek/r8169.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ethernet/realtek/r8169.c 
b/drivers/net/ethernet/realtek/r8169.c
index 7f4647c58..a27bf5807 100644
--- a/drivers/net/ethernet/realtek/r8169.c
+++ b/drivers/net/ethernet/realtek/r8169.c
@@ -4046,16 +4046,13 @@ static void rtl8169_init_phy(struct net_device *dev, 
struct rtl8169_private *tp)
        rtl_hw_phy_config(dev);
 
        if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
+               pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
+               pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
                netif_dbg(tp, drv, dev,
                          "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
                RTL_W8(tp, 0x82, 0x01);
        }
 
-       pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
-
-       if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
-               pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
-
        if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
                netif_dbg(tp, drv, dev,
                          "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
-- 
2.19.0