On 04/17/2018 11:50 AM, Simon Horman wrote:
> From: Kazuya Mizuguchi <kazuya.mizuguchi...@renesas.com>
>
> This patch corrects writing 1 to reserved bits.
> The write value should be 0.
>
> Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi...@renesas.com>
> Signed-off-by: Simon Horman <horms+rene...@verge.net.au>
> ---
> drivers/net/ethernet/renesas/ravb.h | 12 ++++++++++++
> drivers/net/ethernet/renesas/ravb_main.c | 9 +++++----
> drivers/net/ethernet/renesas/ravb_ptp.c | 2 +-
> 3 files changed, 18 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/net/ethernet/renesas/ravb.h
> b/drivers/net/ethernet/renesas/ravb.h
> index b81f4faf7b10..57eea4a77826 100644
> --- a/drivers/net/ethernet/renesas/ravb.h
> +++ b/drivers/net/ethernet/renesas/ravb.h
> @@ -433,6 +433,8 @@ enum EIS_BIT {
> EIS_QFS = 0x00010000,
> };
>
> +#define EIS_RESERVED_BITS (u32)(GENMASK(31, 17) | GENMASK(15, 11))
> +
> /* RIC0 */
> enum RIC0_BIT {
> RIC0_FRE0 = 0x00000001,
> @@ -477,6 +479,8 @@ enum RIS0_BIT {
> RIS0_FRF17 = 0x00020000,
> };
>
> +#define RIS0_RESERVED_BITS (u32)GENMASK(31, 18)
> +
> /* RIC1 */
> enum RIC1_BIT {
> RIC1_RFWE = 0x80000000,
> @@ -533,6 +537,8 @@ enum RIS2_BIT {
> RIS2_RFFF = 0x80000000,
> };
>
> +#define RIS2_RESERVED_BITS (u32)GENMASK_ULL(30, 18)
> +
> /* TIC */
> enum TIC_BIT {
> TIC_FTE0 = 0x00000001, /* Undocumented? */
> @@ -549,6 +555,10 @@ enum TIS_BIT {
> TIS_TFWF = 0x00000200,
> };
>
> +#define TIS_RESERVED_BITS (u32)(GENMASK_ULL(31, 20) | \
> + GENMASK_ULL(15, 12) | \
> + GENMASK_ULL(7, 4))
> +
> /* ISS */
> enum ISS_BIT {
> ISS_FRS = 0x00000001, /* Undocumented? */
> @@ -622,6 +632,8 @@ enum GIS_BIT {
> GIS_PTMF = 0x00000004,
> };
>
> +#define GIS_RESERVED_BITS (u32)GENMASK(15, 10)
> +
> /* GIE (R-Car Gen3 only) */
> enum GIE_BIT {
> GIE_PTCS = 0x00000001,
[...]
Perhaps we can do what the MUSB driver does: declare the writing-zero-clears
masks (inside *enum*!), and then set them before writing th register...
MBR, Sergei
