From: Benjamin Herrenschmidt <[EMAIL PROTECTED]> Date: Sat, 09 Sep 2006 07:46:02 +1000
> I don't think that in general, you have ordering guarantees between > cacheable and non-cacheable stores unless you use explicit barriers. In fact, on most systems you absolutely do have ordering between MMIO and memory accesses. So you are making an extremely poor engineering decision by trying to fixup all the drivers to match PowerPC's semantics. I think a smart engineer would decrease his debugging burdon, by matching his platform's MMIO accessors such that it matches what other platforms do and therefore inheriting the testing coverage provided by all platforms. Otherwise you will be hunting down these kinds of memory barrier issues forever. - To unsubscribe from this list: send the line "unsubscribe netdev" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
