From: Daniel Schultz <d.schu...@phytec.de> Date: Wed, 14 Feb 2018 17:07:11 +0100
> From: Wadim Egorov <w.ego...@phytec.de> > > The DP83867 has a muxing option for the CLK_OUT pin. It is possible > to set CLK_OUT for different channels. > Create a binding to select a specific clock for CLK_OUT pin. > > Signed-off-by: Wadim Egorov <w.ego...@phytec.de> > Signed-off-by: Daniel Schultz <d.schu...@phytec.de> > --- > Changes: > v2: > Added check if clk_output_sel has a valid value > Only write the clock ouput register if a musing is desired > v3: > - Applied to net-next.
