Make sure that PCI write occurs before the delay.
Signed-off-by: Stephen Hemminger <[EMAIL PROTECTED]>
--- sky2.orig/drivers/net/sky2.c 2006-08-28 10:00:17.000000000 -0700
+++ sky2/drivers/net/sky2.c 2006-08-28 10:00:20.000000000 -0700
@@ -531,6 +531,7 @@
reg1 |= phy_power[port];
sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
+ sky2_pci_read32(hw, PCI_DEV_REG1);
udelay(100);
}
@@ -766,9 +767,10 @@
/* Update chip's next pointer */
static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
{
+ q = Y2_QADDR(q, PREF_UNIT_PUT_IDX);
wmb();
- sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
- mmiowb();
+ sky2_write16(hw, q, idx);
+ sky2_read16(hw, q);
}
--
Stephen Hemminger <[EMAIL PROTECTED]>
-
To unsubscribe from this list: send the line "unsubscribe netdev" in
the body of a message to [EMAIL PROTECTED]
More majordomo info at http://vger.kernel.org/majordomo-info.html
