Marc Gonzalez <marc_gonza...@sigmadesigns.com> writes: > On 14/11/2017 14:54, Måns Rullgård wrote: > >> Marc Gonzalez writes: >> >>> On 14/11/2017 13:40, Måns Rullgård wrote: >>> >>>> Marc Gonzalez wrote: >>>> >>>>> Power entire ethernet block down in ndo_stop(). >>>>> Power it back up in ndo_open() and perform HW init. >>>>> Delete nb8800_dma_stop. >>>> >>>> Leave it alone, please. Not all chips might have a separate power >>>> domain for this. Also, it works just fine on the older chips. >>> >>> There is no need for separate power domains. The ethernet block is >>> clock-gated when it is held in reset. >> >> So you're not powering it down then. Please be accurate. > > Smirk. That looks like trolling. > >>> The reset register is implemented on all tango3, tango4, tango5 chips. >> >> It's still not a core feature. > > Correct. But it covers 100% of all chips using this driver. > There is no point in trying to implement support for chips that > have never existed, do not exist, and never will.
You can't know that. >>> nb8800_dma_stop() is a hack. >> >> The hack originated from your company. > > So why are you so insistent that we keep using it? Because it's the only way to support some chip variants. Ones you'd apparently rather forget, but which nonetheless exist. >> Also, I have repeated asked you what happens if the tango5 runs out of >> DMA buffers under normal operation. Does that also cause it to lock up? >> If so, you have a much bigger problem on your hands. > > I will run iperf3 tests with RX_DESC_COUNT lowered to 2. > Would that produce conclusive results? > Do you have other suggestions? Leave RX_DESC_COUNT alone but add a delay in the nb8800_poll() loop. That should ensure that queue is drained slowly enough for the buffers to run out. -- Måns Rullgård
