On Mon, Aug 07, 2006 at 04:35:36PM -0700, Brandeburg, Jesse wrote: > > e1000 only clears the interrupts when it reads ICR in e1000_intr (before > scheduling napi poll) so any interrupts that occur while polling (and > interrupts are disabled) will cause a new assertion once interrupts are > re-enabled. Sometimes a little bit inefficient due to extra trips through > poll, but guarantees never to miss an int. I'm open to creative ways to > avoid this, but adding an I/O read in e1000_clean would be pretty yucky.
The standard solution in Linux is to clear and recheck. So just before you reenable the interrupts you'd clear pending interrupts again and check for rx/tx work, if there is work then you just go back to polling. Cheers, -- Visit Openswan at http://www.openswan.org/ Email: Herbert Xu ~{PmV>HI~} <[EMAIL PROTECTED]> Home Page: http://gondor.apana.org.au/~herbert/ PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt - To unsubscribe from this list: send the line "unsubscribe netdev" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
