From: Vivien Didelot <vivien.dide...@savoirfairelinux.com> Date: Mon, 5 Dec 2016 17:30:24 -0500
> Old Marvell chips (like 88E6060) don't have a PHY Polling Unit (PPU). > > Next chips (like 88E6185) have a PPU, which has exclusive access to the > PHY registers, thus must be disabled before access. > > Newer chips (like 88E6352) have an indirect mechanism to access the PHY > registers whenever, thus loose control over the PPU (always enabled). > > Here's a summary: > > Model | PPU? | Has PPU ctrl? | PPU state readable? | PHY access > ----- | ---- | -------------- | ------------------- | ---------- > 6060 | no | no | no | direct > 6185 | yes | yes, PPUEn bit | yes, PPUState 2-bit | direct w/ PPU dis. > 6352 | yes | no | yes, PPUState 1-bit | indirect > 6390 | yes | no | yes, InitState bit | indirect > > Depending on the PPU control, a switch may have to restart the PPU when > resetting the switch. Once the switch is reset, we must wait for the PPU > state to be active polling again before accessing the registers. > > For that purpose, add new operations to the chips to enable/disable the > PPU, and execute software reset. With these new ops in place, rework the > switch reset code and finally get rid of the MV88E6XXX_FLAG_PPU* flags. Series applied, thanks Vivien. And thanks for the detailed, informative, header postings like this one.
