Le 27/11/2016 à 14:24, Timur Tabi a écrit : >> + * PHY device drivers in PHYLIB being reusable by nature, being able to >> + configure correctly a specified delay enables more designs with >> similar delay >> + requirements to be operate correctly > > Ok, this one I don't know how to fix. I'm not really sure what you're > trying to say.
What I am trying to say is that once a PHY driver properly configures a delay that you have specified, there is no reason why this is not applicable to other platforms using this same PHY driver. >> + >> +Common problems with RGMII delay mismatch >> + >> + When there is a RGMII delay mismatch between the Ethernet MAC and >> the PHY, this >> + will most likely result in the clock and data line sampling to >> capture unstable > > I'm not sure what "sampling to capture unstable" is supposed to mean. When the PHY devices takes a "snapshot" of the state of the data lines, after a clock edge, if the delay is improperly configured, these data lines are going to still be floating, or show some kind of capacitance/inductance effect, so the logical level which is going to be read may be incorrect. -- Florian
