Hello,
I think, there could a bug in your patch.
> +
> +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
> + dmacfg |= GEM_BIT(ADDR64);
> +#endif
You enable 64 bit addressing (64b dma bus width) always when appropriate
architecture config option is enabled.
But there are some legacy controllers which do not support that feature.
According Cadence hardware team:
"64 bit addressing was added in July 2013. Earlier version do not have it.
This feature was enhanced in release August 2014 to have separate upper address
values for transmit and receive."
> /* Bitfields in NSR */
> @@ -474,6 +479,10 @@
> struct macb_dma_desc {
> u32 addr;
> u32 ctrl;
> +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
> + u32 addrh;
> + u32 resvd;
> +#endif
> };
It will not work for legacy hardware. Old descriptor is 2 words wide, the new
one is 4 words wide.
If you enable CONFIG_ARCH_DMA_ADDR_T_64BIT but hardware doesn't support it at
all,
you will miss every second descriptor.
Regards,
Rafal
