From: Qianqian Xie <xieqianq...@huawei.com>
As the user manual describs, XGE_DFX_CTRL_CFG.xge_dfx_ctrl_cfg should be
configed as zero if we want xge statistic reg to be read only. But the
older hisilicon arm64 process gets the other meanings. So it seems that
we need to identify the process and then config it rightly.
Signed-off-by: Qianqian Xie <xieqianq...@huawei.com>
---
drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c
b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c
index 9439f04..7fe1c1c 100644
--- a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c
+++ b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c
@@ -714,8 +714,9 @@ static void hns_dsaf_tbl_stat_en(struct dsaf_device
*dsaf_dev)
*/
static void hns_dsaf_rocee_bp_en(struct dsaf_device *dsaf_dev)
{
- dsaf_set_dev_bit(dsaf_dev, DSAF_XGE_CTRL_SIG_CFG_0_REG,
- DSAF_FC_XGE_TX_PAUSE_S, 1);
+ if (AE_IS_VER1(dsaf_dev->dsaf_ver))
+ dsaf_set_dev_bit(dsaf_dev, DSAF_XGE_CTRL_SIG_CFG_0_REG,
+ DSAF_FC_XGE_TX_PAUSE_S, 1);
}
/* set msk for dsaf exception irq*/
--
1.9.1
