On Thu, 2006-03-23 at 16:41 -0800, David S. Miller wrote: > It might not be wise to be putting the chip into D0 state by hand as > we are doing there. For example, that bare minimal sequence we added > doesn't swith out of Vaux like tg3_set_power_state() does.
It's a bit of a chicken and egg problem. We don't know whether we should switch out of Vaux or not until we read the SRAM contents. After we're done with tg3_get_eeprom_hw_cfg(), we will promptly switch to D0 (again) and switch out of Vaux if required. > > Also, that new code does does not set the PCI_PM_CTRL_PME_STATUS bit > which tg3_set_power_state() unconditionally does. > I don't think this bit matters a whole lot at this point in the probe sequence. Setting the bit will clear the PME status if it was asserted to wakeup the system so that the device can generate PME# again. - To unsubscribe from this list: send the line "unsubscribe netdev" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
