David S. Miller wrote: > From: Christoph Hellwig <[EMAIL PROTECTED]> > Date: Sat, 18 Mar 2006 06:16:31 +0000 > > > That workaround should be in the pci code as it affects any pci > > device behind that bridge, not just tg3 ones. > > We don't have any infrastructure to do that, even if it > was practical.
Plus in practice, only tg3 devices will be affected. The 4-port NIC designs all use 5704 behind the bridge and nothing else. Same for the Niagara erie system, but sparc64 uses 32-bit DMA as David pointed out to me, so it's not an issue at all. There are some x86 designs where a PCIX bus is put behind the EPB, but x86 will never address higher than 40-bit. At this point, I am only aware of some IA64 systems such as those from SGI that require the workaround when using the Silicom 4-port NIC. - To unsubscribe from this list: send the line "unsubscribe netdev" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
