OKOK. forgot the attachment!
Arnd-Hendrik Mathias wrote:
Hi John,
have you already found some solution for your dependencies problem (OK
it's almost one month ago)? If not so you can have a look at this brief
example makefile. It generates one xxx.d file in obj/ for each xxx.o
file in obj/ depending on xxx.c in src/. This is just to demonstrate the
-MF and -MT option (line 20). There is a pcket full of other options
like p.e. -MD (together with -o) but for me this combination always
produces an additional empty xxx.o which in further make process is
younger than the xxx.c file and thus xxx.c is not recompiled.
Good luck
Arnd-Hendrik
John Glendenning wrote:
Hi Everybody,
Here's what I want to do...
I have c source files in several directories, and I want the object
files created from these files to be placed in a single directory. I
am using the following in my makefile,
dependencies.in:
$(CC) -MM ${CFLAGS} $(SOURCES) > $@
where CFLAGS has the usual meaning and SOURCES is a list of all the c
source files, (with path information). The problem is that the
dependencies.in file created from this command places the object files
in the same directory as the c file it is made from. Also the default
rule no longer applies because the object and c files are not together.
How can I create dependencies.in with the correct information?
Thanks
John
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CC := msp430-gcc
CCFLAGS := -mmcu=msp430x169
SRCPATH := src
OBJPATH := obj
SOURCES := $(wildcard $(SRCPATH)/*.c)
MODULES := $(basename $(notdir $(SOURCES)))
OBJECT := $(OBJPATH)/demo.elf
OBJECTS := $(addprefix $(OBJPATH)/, $(addsuffix .o, $(MODULES)))
DEPENDS := $(addprefix $(OBJPATH)/, $(addsuffix .d, $(MODULES)))
.PHONY : clean default
default: $(DEPENDS)
$(MAKE) $(OBJECT)
clean:
rm $(wildcard $(OBJPATH)/*)
$(DEPENDS) : $(OBJPATH)/%.d: $(SRCPATH)/%.c
$(CC) -M -MF $@ -MT $(@:.d=.o) $^
$(OBJECT): $(OBJECTS)
$(CC) $(CCFLAGS) -o $@ $^
$(OBJECTS) : $(OBJPATH)/%.o: $(SRCPATH)/%.c
$(CC) -c $(CCFLAGS) -o $@ $<
-include $(DEPENDS)
