OK,
neither r2 nor r3 being used by gcc during code generation.
instruction 'nop' however is mov #0,r3
and r2 being used twice as follows:
1.when loosing LPM
bic #0xf0,r2
2. and in __stopProg_Exec__
bis #0xf0, r2
both are safe... I hope...
~d
On Fri, 30 Aug 2002 09:35:57 +0200
"David Brown" <[email protected]> wrote:
> I saw this post on the ImageCraft icc-430 mailing list (I follow both
> lists - occasionally it can be useful to cross-polinate). Do you guys know
> about these problems (or supposed problems) ?
>
> ----- Original Message -----
> From: <[email protected]>
> To: <[email protected]>
> Sent: Friday, August 30, 2002 1:58 AM
> Subject: [Icc-430] R2 and R3 operations
>
>
> > TI's doucmentation to the contrary, operations on R2
> > do affect the status values. However, while performing
> > these operations, the MSP's internal status checking is
> > disabled so that common sense results are obtained.
> > For instance, clearing R2 does /not/ set the Z bit to
> > indicate that zero was written to R2. Other than
> > disabling the status actions, operations on R2 are the
> > same as any for other register.
> >
> > Performing operations on R3 gives very peculiar results
> > including throwing the processor into some interminable
> > wild state. It would seem to be the better part of
> > discretion to avoid trying to write to R3 and just use
> > it in its CG2 role only.
> >
> > ----------------------------------------------------------------------
> > Everett M. Greene (The Mojave Greene, crotalus scutulatus scutulatus)
> > Ridgecrest, Ca. 93555 Path: [email protected]
> >
> > The 50-50-90 rule: Anytime you have a 50-50 chance of getting
> > something right, there's a 90% probability you'll get it wrong.
> >
> >
> > _______________________________________________
> > Icc-430 mailing list
> > [email protected]
> > http://www.dragonsgate.net/mailman/listinfo/icc-430
> >
>
>
>
>
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