On Thu, Jul 17, 2025 at 03:58:36PM +1000, Jonathan Gray wrote:
> On Thu, Jul 17, 2025 at 02:08:13PM +1000, Jonathan Gray wrote:
> > On Thu, Jul 17, 2025 at 03:00:15PM +1200, Avon Robertson wrote:
> > > This machine was out of service for several weeks. When it re-entered
> > > service with 2 new spinning disks, OpenBSD was reinstalled from a
> > > slightly outdated install77.img. It was promptly <sysupgrade'd -s> and
> > > current- new packages were installed. Since then, 2 more
> > > 'sysupgrade -s' and 'pkg_add -Dsnap -uv' cycles have occurred.
> > >
> > > >From re-entry to service the machine will not enter the X Windows System.
> > >
[ snip ... ]
>
> Try rebuild xenocara with the following patch.
>
> reverts the 25.0 backport of:
> radeonsi: always lower alu bit sizes
> 2d525d5e3401555d97fe827f8db5bfed8887dc33
>
> cherry picks:
>
> radv: don't use bit_sizes_int to skip nir_lower_bit_size
> f034aa9cd31ea4aa367f8ed58bd270026abf748e
>
> radeonsi: always lower alu bit sizes
> 33b5d8b2ec26904ec1c331dd64ee04e351fd8e0e
>
> Index: lib/mesa/src/amd/common/nir/ac_nir.c
> ===================================================================
> RCS file: /cvs/xenocara/lib/mesa/src/amd/common/nir/ac_nir.c,v
> diff -u -p -r1.1.1.1 ac_nir.c
> --- lib/mesa/src/amd/common/nir/ac_nir.c 5 Jun 2025 11:26:30 -0000
> 1.1.1.1
> +++ lib/mesa/src/amd/common/nir/ac_nir.c 17 Jul 2025 05:41:07 -0000
> @@ -340,11 +340,9 @@ ac_nir_optimize_uniform_atomics(nir_shad
> return progress;
> }
>
> -unsigned
> -ac_nir_lower_bit_size_callback(const nir_instr *instr, void *data)
> +static unsigned
> +lower_bit_size_callback(const nir_instr *instr, enum amd_gfx_level chip,
> bool divergence_known)
> {
> - enum amd_gfx_level chip = *(enum amd_gfx_level *)data;
> -
> if (instr->type != nir_instr_type_alu)
> return 0;
> nir_alu_instr *alu = nir_instr_as_alu(instr);
> @@ -374,10 +372,10 @@ ac_nir_lower_bit_size_callback(const nir
> case nir_op_isign:
> case nir_op_uadd_sat:
> case nir_op_usub_sat:
> - return (bit_size == 8 || !(chip >= GFX8 && alu->def.divergent)) ?
> 32 : 0;
> + return (!divergence_known || bit_size == 8 || !(chip >= GFX8 &&
> alu->def.divergent)) ? 32 : 0;
> case nir_op_iadd_sat:
> case nir_op_isub_sat:
> - return bit_size == 8 || !alu->def.divergent ? 32 : 0;
> + return !divergence_known || bit_size == 8 || !alu->def.divergent ?
> 32 : 0;
>
> default:
> return 0;
> @@ -399,13 +397,35 @@ ac_nir_lower_bit_size_callback(const nir
> case nir_op_uge:
> case nir_op_bitz:
> case nir_op_bitnz:
> - return (bit_size == 8 || !(chip >= GFX8 && alu->def.divergent)) ?
> 32 : 0;
> + return (!divergence_known || bit_size == 8 || !(chip >= GFX8 &&
> alu->def.divergent)) ? 32 : 0;
> default:
> return 0;
> }
> }
>
> return 0;
> +}
> +
> +unsigned
> +ac_nir_lower_bit_size_callback(const nir_instr *instr, void *data)
> +{
> + enum amd_gfx_level chip = *(enum amd_gfx_level *)data;
> + return lower_bit_size_callback(instr, chip, true);
> +}
> +
> +bool
> +ac_nir_might_lower_bit_size(const nir_shader *shader)
> +{
> + nir_foreach_function_impl(impl, shader) {
> + nir_foreach_block(block, impl) {
> + nir_foreach_instr(instr, block) {
> + if (lower_bit_size_callback(instr, CLASS_UNKNOWN, false))
> + return true;
> + }
> + }
> + }
> +
> + return false;
> }
>
> static unsigned
> Index: lib/mesa/src/amd/common/nir/ac_nir.h
> ===================================================================
> RCS file: /cvs/xenocara/lib/mesa/src/amd/common/nir/ac_nir.h,v
> diff -u -p -r1.1.1.1 ac_nir.h
> --- lib/mesa/src/amd/common/nir/ac_nir.h 5 Jun 2025 11:26:30 -0000
> 1.1.1.1
> +++ lib/mesa/src/amd/common/nir/ac_nir.h 17 Jul 2025 05:41:07 -0000
> @@ -397,6 +397,9 @@ unsigned
> ac_nir_lower_bit_size_callback(const nir_instr *instr, void *data);
>
> bool
> +ac_nir_might_lower_bit_size(const nir_shader *shader);
> +
> +bool
> ac_nir_mem_vectorize_callback(unsigned align_mul, unsigned align_offset,
> unsigned bit_size,
> unsigned num_components, int64_t hole_size,
> nir_intrinsic_instr *low, nir_intrinsic_instr
> *high, void *data);
> Index: lib/mesa/src/amd/vulkan/radv_pipeline.c
> ===================================================================
> RCS file: /cvs/xenocara/lib/mesa/src/amd/vulkan/radv_pipeline.c,v
> diff -u -p -r1.22 radv_pipeline.c
> --- lib/mesa/src/amd/vulkan/radv_pipeline.c 5 Jun 2025 14:18:54 -0000
> 1.22
> +++ lib/mesa/src/amd/vulkan/radv_pipeline.c 17 Jul 2025 05:41:07 -0000
> @@ -352,9 +352,6 @@ radv_postprocess_nir(struct radv_device
> NIR_PASS(_, stage->nir, nir_opt_shrink_stores,
> !instance->drirc.disable_shrink_image_store);
>
> constant_fold_for_push_const = true;
> -
> - /* Gather info again, to update whether 8/16-bit are used. */
> - nir_shader_gather_info(stage->nir,
> nir_shader_get_entrypoint(stage->nir));
> }
> }
>
> @@ -533,7 +530,7 @@ radv_postprocess_nir(struct radv_device
>
> NIR_PASS(_, stage->nir, nir_lower_fp16_casts, nir_lower_fp16_split_fp64);
>
> - if (stage->nir->info.bit_sizes_int & (8 | 16)) {
> + if (ac_nir_might_lower_bit_size(stage->nir)) {
> if (gfx_level >= GFX8)
> nir_divergence_analysis(stage->nir);
>
> Index: lib/mesa/src/gallium/drivers/radeonsi/si_shader.c
> ===================================================================
> RCS file: /cvs/xenocara/lib/mesa/src/gallium/drivers/radeonsi/si_shader.c,v
> diff -u -p -r1.18 si_shader.c
> --- lib/mesa/src/gallium/drivers/radeonsi/si_shader.c 5 Jun 2025 14:19:19
> -0000 1.18
> +++ lib/mesa/src/gallium/drivers/radeonsi/si_shader.c 17 Jul 2025 05:41:07
> -0000
> @@ -2556,7 +2556,7 @@ static void run_late_optimization_and_lo
> if (nir->info.stage == MESA_SHADER_KERNEL)
> NIR_PASS(progress, nir, ac_nir_lower_global_access);
>
> - if (nir->info.bit_sizes_int & (8 | 16)) {
> + if (ac_nir_might_lower_bit_size(nir)) {
> if (sel->screen->info.gfx_level >= GFX8)
> nir_divergence_analysis(nir);
>
>
Tomorrow I will apply your patch and rebuild xenocara. I will post the
results after the rebuild.
