Hello Stefan,
On Mon, May 29, 2023 at 09:07:09PM +0200, Stefan Sperling wrote:
> On Mon, May 29, 2023 at 10:13:30PM +1200, Avon Robertson wrote:
> > $ fgrep -e AR9485 *
> > ar9003reg.h:#define AR9485_PHY_65NM_CH0_TOP2 0x16284
> > ar9003reg.h:#define AR9485_PHY_CH0_XTAL 0x16290
> > ar9003reg.h:/* Bits for AR9485_PHY_65NM_CH0_TOP2. */
> > ar9003reg.h:#define AR9485_PHY_65NM_CH0_TOP2_XPABIASLVL_M 0x0000f000
> > ar9003reg.h:#define AR9485_PHY_65NM_CH0_TOP2_XPABIASLVL_S 12
> > ar9003reg.h:/* Bits for AR9485_PHY_CH0_XTAL. */
> > ar9003reg.h:#define AR9485_PHY_CH0_XTAL_CAPINDAC_M 0x7f000000
> > ar9003reg.h:#define AR9485_PHY_CH0_XTAL_CAPINDAC_S 24
> > ar9003reg.h:#define AR9485_PHY_CH0_XTAL_CAPOUTDAC_M 0x00fe0000
> > ar9003reg.h:#define AR9485_PHY_CH0_XTAL_CAPOUTDAC_S 17
> > ar9380.c: * Routines for AR9380 and AR9485 chipsets.
> > ar9380.c: reg = AR_READ(sc, AR9485_PHY_65NM_CH0_TOP2);
> > ar9380.c: reg = RW(reg, AR9485_PHY_65NM_CH0_TOP2_XPABIASLVL,
> > ar9380.c: AR_WRITE(sc, AR9485_PHY_65NM_CH0_TOP2, reg);
> > ar9380.c: reg = AR_READ(sc, AR9485_PHY_CH0_XTAL);
> > ar9380.c: reg = RW(reg, AR9485_PHY_CH0_XTAL_CAPINDAC,
> > ar9380.c: reg = RW(reg, AR9485_PHY_CH0_XTAL_CAPOUTDAC,
> > ar9380.c: AR_WRITE(sc, AR9485_PHY_CH0_XTAL, reg);
> > ar9380reg.h: * AR9485 1.1 programming.
> > ar9380reg.h: * AR9485 1.1 Tx gains.
> > ar9380reg.h: * AR9485 1.1 Rx gains.
> > athn.c: return ("AR9485");
> >
> > Am I missing something w.r.t. enabling the athn interface OR is the
> > Atheros AR9485 chip really unsupported? The dmesg output identifies it
> > as having a rom address conflict and as having an unconfigured function
> > 0.
>
> The ar9380.c parts of this driver are intentionally disabled because they
> do not work. I would be happy to review and test patches that improve
> this sad situation.
Thank you for the information. I will look further into the issue in a
few days when time permits, and try to gain some understanding of the
driver code.
--
Regards,
aer
