Le 03/06/2013 13:57, Kai Tietz a écrit :
> 2013/6/3 dw <limegreenso...@yahoo.com>:
>> 3) Use code like:
>>
>> __MINGW_INTRIN_INLINE void x__faststorefence(void) {
>>
>> #ifdef __SSE__ // defined by gcc when sse instructions are available
>> asm ("sfence" ::: "memory");
>> #else
>> asm ("lock or %[zero], (%%rsp)" :: [zero] "ri" (0) : "memory", "cc");
>> #endif
>>
>> }
>>
>> Pros:
>> - Uses the faster sfence if available.
>> - Falls back to "or" for max compatibility.
>>
>> cons:
>> - Not consistent with MSVC.
>> - SFENCE is not necessarily the fastest on all processors.
>>
>> I ran some timings using x64 on my i7, and this is what I find:
>>
>> _mm_sfence: 3,589,817,193
>> lock or : 14,960,719,245
>> _mm_mfence: 19,608,594,657
>>
>> Obviously these results are going to be both highly hw specific and depend
>> heavily on the code surrounding them. Still...
>>
>> If I were going to pick, I'd probably go with #3. It isn't 100% identical
>> to MSVC, but it effectively produces the same results, and will (at least on
>> current processors) generate faster code.
>>
>> Opinions?
>>
>> dw
>
> I think option #3 is that one I prefer too. Just one thing about
> SSE-instruction. For 64-bit we can assume that SSE has to be present
> in any case. Just for 32-bit we should check in headers for the
> __SSE__ macro, and in the intrinsic-function (none-inline) we should
> default to none-SSE version.
__SSE__ should always be defined with x86_64 so just checking for
__SSE__ might be simpler and will give the fastest version.
Thus the same definition could be used for both inline and intrinsic.
> Kai
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