We only need the batch promotion for secure dispatch if we need to modify privileged registers, so only request it when we do register loads and stores.
Signed-off-by: Chris Wilson <[email protected]> --- src/mesa/drivers/dri/i965/brw_batch.c | 12 ++++++++++-- src/mesa/drivers/dri/i965/brw_batch.h | 2 ++ src/mesa/drivers/dri/i965/brw_pipelined_register.c | 3 +++ src/mesa/drivers/dri/i965/intel_blit.c | 1 + 4 files changed, 16 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_batch.c b/src/mesa/drivers/dri/i965/brw_batch.c index 36a0890..927911f 100644 --- a/src/mesa/drivers/dri/i965/brw_batch.c +++ b/src/mesa/drivers/dri/i965/brw_batch.c @@ -107,6 +107,8 @@ #define WRITE_SIGNAL 1 #define NO_SIGNAL 2 +#define BATCH_FLAGS (~(LOCAL_BATCH_ENABLE_MMIO)) + static const unsigned hw_ring[] = { [RENDER_RING] = I915_EXEC_RENDER, [BLT_RING] = I915_EXEC_BLT, @@ -591,6 +593,9 @@ int brw_batch_init(struct brw_batch *batch, batch->no_hw = screen->no_hw; + if (devinfo->is_haswell) + batch->length_flag = LOCAL_BATCH_ENABLE_MMIO; + batch->needs_pipecontrol_ggtt_wa = devinfo->gen == 6; batch->reloc_size = 512; batch->exec_size = 256; @@ -950,7 +955,10 @@ static uint32_t __brw_batch_finish(struct brw_batch *batch, } batch->map[batch->emit.nbatch] = 0xa << 23; - return 4*((batch->emit.nbatch + 2) & ~1); + if (batch->batch_flags & batch->length_flag) + return 4*((batch->emit.nbatch + 2) & ~1); + else + return 0; } static void @@ -1112,7 +1120,7 @@ int brw_batch_flush(struct brw_batch *batch, struct perf_debug *perf) execbuf.buffer_count = batch->emit.nexec; if (batch->ring == RENDER_RING || batch->has_softpin) execbuf.rsvd1 = batch->hw_ctx; - execbuf.flags = hw_ring[batch->ring] | batch->batch_flags; + execbuf.flags = hw_ring[batch->ring] | (batch->batch_flags & BATCH_FLAGS); if (unlikely(batch->no_hw)) goto skip; diff --git a/src/mesa/drivers/dri/i965/brw_batch.h b/src/mesa/drivers/dri/i965/brw_batch.h index 5de1209..299c7b7 100644 --- a/src/mesa/drivers/dri/i965/brw_batch.h +++ b/src/mesa/drivers/dri/i965/brw_batch.h @@ -106,7 +106,9 @@ typedef struct brw_batch { uint32_t *_ptr; uint32_t batch_flags; +#define LOCAL_BATCH_ENABLE_MMIO (1<<31) uint32_t batch_base_flags; + uint32_t length_flag; enum brw_gpu_ring ring; uint32_t hw_ctx; diff --git a/src/mesa/drivers/dri/i965/brw_pipelined_register.c b/src/mesa/drivers/dri/i965/brw_pipelined_register.c index 727c571..83f4672 100644 --- a/src/mesa/drivers/dri/i965/brw_pipelined_register.c +++ b/src/mesa/drivers/dri/i965/brw_pipelined_register.c @@ -46,6 +46,7 @@ load_sized_register_mem(struct brw_context *brw, OUT_BATCH(reg + i * 4); OUT_RELOC64(bo, domains, offset + i * 4); } + brw->batch.batch_flags |= LOCAL_BATCH_ENABLE_MMIO; ADVANCE_BATCH(); } else { BEGIN_BATCH(3 * size); @@ -54,6 +55,7 @@ load_sized_register_mem(struct brw_context *brw, OUT_BATCH(reg + i * 4); OUT_RELOC(bo, domains, offset + i * 4); } + brw->batch.batch_flags |= LOCAL_BATCH_ENABLE_MMIO; ADVANCE_BATCH(); } } @@ -87,5 +89,6 @@ brw_load_register_imm(struct brw_context *brw, OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2)); OUT_BATCH(reg); OUT_BATCH(value); + brw->batch.batch_flags |= LOCAL_BATCH_ENABLE_MMIO; ADVANCE_BATCH(); } diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c index 845fcde..b46d268 100644 --- a/src/mesa/drivers/dri/i965/intel_blit.c +++ b/src/mesa/drivers/dri/i965/intel_blit.c @@ -193,6 +193,7 @@ set_blitter_tiling(struct brw_context *brw, OUT_BATCH((BCS_SWCTRL_DST_Y | BCS_SWCTRL_SRC_Y) << 16 | (dst_y_tiled ? BCS_SWCTRL_DST_Y : 0) | (src_y_tiled ? BCS_SWCTRL_SRC_Y : 0)); + brw->batch.batch_flags |= LOCAL_BATCH_ENABLE_MMIO; return __map; } #define SET_BLITTER_TILING(...) __map = set_blitter_tiling(__VA_ARGS__, __map) -- 2.5.0 _______________________________________________ mesa-dev mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/mesa-dev
