From: Antia Puentes <[email protected]>
Adds NIR ALU operations:
* nir_op_ball_fequal2
* nir_op_ball_iequal2
* nir_op_ball_fequal3
* nir_op_ball_iequal3
* nir_op_ball_fequal4
* nir_op_ball_iequal4
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 33 ++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index dc8b082..4562f7d 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -925,6 +925,39 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
brw_conditional_for_nir_comparison(instr->op)));
break;
+ case nir_op_ball_fequal2:
+ case nir_op_ball_iequal2:
+ case nir_op_ball_fequal3:
+ case nir_op_ball_iequal3:
+ case nir_op_ball_fequal4:
+ case nir_op_ball_iequal4: {
+ dst_reg tmp = dst_reg(this, glsl_type::bool_type);
+
+ switch (instr->op) {
+ case nir_op_ball_fequal2:
+ case nir_op_ball_iequal2:
+ tmp.writemask = WRITEMASK_XY;
+ break;
+ case nir_op_ball_fequal3:
+ case nir_op_ball_iequal3:
+ tmp.writemask = WRITEMASK_XYZ;
+ break;
+ case nir_op_ball_fequal4:
+ case nir_op_ball_iequal4:
+ tmp.writemask = WRITEMASK_XYZW;
+ break;
+ default:
+ unreachable("not reached");
+ }
+
+ emit(CMP(tmp, op[0], op[1],
+ brw_conditional_for_nir_comparison(instr->op)));
+ emit(MOV(dst, src_reg(0)));
+ inst = emit(MOV(dst, src_reg(~0)));
+ inst->predicate = BRW_PREDICATE_ALIGN16_ALL4H;
+ break;
+ }
+
default:
unreachable("Unimplemented ALU operation");
}
--
2.1.4
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