From: Nanley Chery <nanley.g.ch...@intel.com>
In agreement with commit 4ab8d59a23, vertical alignment values are equal to
four times the block height on Gen9+.
v2: add newlines to separate declarations, statments, and comments.
Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>
Reviewed-by: Neil Roberts <n...@linux.intel.com>
Signed-off-by: Nanley Chery <nanley.g.ch...@intel.com>
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 4007697..ade2940 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -270,9 +270,14 @@ intel_vertical_texture_alignment_unit(struct brw_context
*brw,
* Where "*" means either VALIGN_2 or VALIGN_4 depending on the setting of
* the SURFACE_STATE "Surface Vertical Alignment" field.
*/
- if (_mesa_is_format_compressed(mt->format))
- /* See comment above for the horizontal alignment */
- return brw->gen >= 9 ? 16 : 4;
+ if (_mesa_is_format_compressed(mt->format)) {
+ unsigned int i, j;
+
+ _mesa_get_format_block_size(mt->format, &i, &j);
+
+ /* See comment above for the horizontal alignment */
+ return brw->gen >= 9 ? j * 4 : 4;
+ }
if (mt->format == MESA_FORMAT_S_UINT8)
return brw->gen >= 7 ? 8 : 4;
--
2.4.2
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