Several steppings of Skylake fail when using SIMD16 with 3-source
instructions (such as MAD).
This implements WaDisableSIMD16On3SrcInstr and fixes ~190 Piglit
tests.
Based on a patch by Neil Roberts.
Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
Cc: Neil Roberts <n...@linux.intel.com>
Cc: Matt Turner <matts...@gmail.com>
---
src/mesa/drivers/dri/i965/brw_shader.cpp | 6 ++++++
1 file changed, 6 insertions(+)
Neil, what do you think of this approach? It's a bit smaller of a hammer
than turning off SIMD16 altogether, and pretty simple. I haven't tested
it at all, though.
Feel free to --reset-author and claim authorship on this patch - it's
really your code, I just moved it over a bit.
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index fed4ba3..74c0e50 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -400,6 +400,12 @@ bool
brw_instruction_supports_simd16(const struct brw_context *brw, enum opcode op)
{
bool supports_3src = brw->is_haswell || brw->gen >= 8;
+ /* WaDisableSIMD16On3SrcInstr: 3-source instructions don't work in SIMD16
+ * on a few steppings of Skylake.
+ */
+ if (brw->gen == 9 && (brw->revision == 2 || brw->revision == 3 ||
+ brw->revision == -1))
+ supports_3src = false;
switch (op) {
case BRW_OPCODE_MAD:
--
2.2.2
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