Does anyone have any information related to the Surface Sync PM4 command and the output from DRM?
I am having issues with CP stalls and am trying to figure out what is not getting satisfied. Unfortunately the Radeon docs all say 'see the CP_COHER_CNTL register for a definition' - but I have not yet found any documentation for this register in the R600/R700 or Evergreen documents that I have found. Thanks, Al Dorrington Software Engineer Sr Lockheed Martin, Mission Systems and Training
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