Hi all, I've been digging through the i965 driver implementation attempting to get my head around it. I have a few questions which I hope can be answered:
* What is LIR? The comments say that Mesa GLSL IR is converted into LIR which in turn is converted into GPU code. What is LIR and how is the LIR represented? I am guessing LIR is some intermediate thing used by i965 before going to code for different GPUs supported on the i965 or "Lower IR" from Mesa upstairs. * In brw_misc_state.c, why does brw_workaround_depthstencil_alignment() even exist? I understand the work around issue, but why are not those buffers allocated so that they are aligned? Moreover, I did not really understand the remark for Gen7 hardware: "Gen7+ doesn't require the workarounds, since we always program the surface state at the start of the whole surface." not needing the workaround, is that comment talking about a specific brw_state_tracker in gen7_atoms (of brw_state_upload) or about how the memory is allocated or something else? Best Regards -Kevin Rogovin _______________________________________________ mesa-dev mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/mesa-dev
