IBs need to be a multiple of 4 dwords on r6xx asics to avoid a hw bug. Also align IBs to 8 DW to align with the fetch size of the CP.
v2: apply to all asics, increase alignment to 8 Signed-off-by: Alex Deucher <[email protected]> CC: "9.2" <[email protected]> CC: "9.1" <[email protected]> --- src/gallium/drivers/r600/r600_hw_context.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c index 97b0f9c..8113f1c 100644 --- a/src/gallium/drivers/r600/r600_hw_context.c +++ b/src/gallium/drivers/r600/r600_hw_context.c @@ -309,6 +309,7 @@ void r600_flush_emit(struct r600_context *rctx) void r600_context_flush(struct r600_context *ctx, unsigned flags) { struct radeon_winsys_cs *cs = ctx->rings.gfx.cs; + unsigned i, padding_dw; ctx->nontimer_queries_suspended = false; ctx->streamout.suspended = false; @@ -347,6 +348,17 @@ void r600_context_flush(struct r600_context *ctx, unsigned flags) flags |= RADEON_FLUSH_KEEP_TILING_FLAGS; } + /* Pad the GFX CS to a multiple of 8 dwords to + * align with CP fetch requirements. rv6xx + * requires at least 4 DW alignment to avoid a hw bug. + */ + padding_dw = 8 - cs->cdw % 8; + if (padding_dw < 8) { + for (i = 0; i < padding_dw; i++) { + cs->buf[cs->cdw++] = 0x80000000; + } + } + /* Flush the CS. */ ctx->ws->cs_flush(ctx->rings.gfx.cs, flags, ctx->screen->cs_count++); } -- 1.8.3.1 _______________________________________________ mesa-dev mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/mesa-dev
