On 07/18/2013 12:10 AM, Kenneth Graunke wrote:
The L3 controls are identical on all platforms, but LLC differs:
- Ivybridge has a "cache in LLC" flag
- Baytrail has no LLC, but instead has a snoop bit:
"data accesses in this page must be snooped in the CPU caches."
- Haswell has writeback/uncached flags for LLC and eLLC (eDRAM).
Signed-off-by: Kenneth Graunke <[email protected]>
Cc: Chad Versace <[email protected]>
---
src/mesa/drivers/dri/i965/brw_defines.h | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index 04422fe..db63b2b 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1728,6 +1728,20 @@ enum brw_wm_barycentric_interp_mode {
*/
#define BRW_MAX_NUM_BUFFER_ENTRIES (1 << 27)
+/* Memory Object Control State */
+#define GEN7_MOCS_L3 1
+
+/* Ivybridge only: cache in LLC */
+#define IVB_MOCS_LLC (1 << 1)
+
+/* Baytrail only: snoop in CPU cache */
+#define BYT_MOCS_SNOOP (1 << 1)
+
+/* Haswell only: LLC/eLLC controls (write-back or uncached) */
+#define HSW_MOCS_UC_LLC_UC_ELLC (1 << 1)
+#define HSW_MOCS_WB_LLC_WB_ELLC (2 << 1)
+#define HSW_MOCS_UC_LLC_WB_ELLC (3 << 1)
I like these names better than my names. But...
The significance of dw0[0]=0 and dw0[1:2]=0, on both ivb and hsw, differ
greatly.
But that difference is not apparent from the token names nor the comments.
dw0[0]=0 means "uncacheable in L3", but dw0[1:2]=0 means "use the cacheability
controls from the PTE".
Please add some brief comments to that effect in the patch. Otherwise, I think
misunderstanding that difference will be a very easy, and frequent, mistake
made by many of us, including my future self.
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