Chad Versace <[email protected]> writes: > On 04/09/2013 04:03 PM, Eric Anholt wrote: >> Kenneth Graunke <[email protected]> writes: >> >>> From: Chad Versace <[email protected]> >>> >>> On Haswell, HiZ will selectively be enabled on individual miptree slices >>> to workaround a hardware bug. The two new functions below will permit us >>> to detect if hiz is enabled for a particular slice. >>> >>> intel_miptree_slice_has_hiz >>> intel_renderbuffer_has_hiz >>> >>> The functions are not yet used. >>> >>> Signed-off-by: Chad Versace <[email protected]> >>> --- >>> src/mesa/drivers/dri/intel/intel_fbo.c | 10 ++++++++++ >>> src/mesa/drivers/dri/intel/intel_fbo.h | 3 +++ >>> src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 12 ++++++++++++ >>> src/mesa/drivers/dri/intel/intel_mipmap_tree.h | 11 +++++++++-- >>> 4 files changed, 34 insertions(+), 2 deletions(-) >>> >>> diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c >>> b/src/mesa/drivers/dri/intel/intel_fbo.c >>> index 2977568..0e2ded5 100644 >>> --- a/src/mesa/drivers/dri/intel/intel_fbo.c >>> +++ b/src/mesa/drivers/dri/intel/intel_fbo.c >>> @@ -943,6 +943,16 @@ intel_renderbuffer_set_needs_downsample(struct >>> intel_renderbuffer *irb) >>> irb->mt->need_downsample = true; >>> } >>> >>> +/** >>> + * Does the renderbuffer have hiz enabled? >>> + */ >>> +bool >>> +intel_renderbuffer_has_hiz(struct intel_renderbuffer *irb) >>> +{ >>> + return irb->mt && >>> + intel_miptree_slice_has_hiz(irb->mt, irb->mt_level, >>> irb->mt_layer); >>> +} >> >> irb->mt should always be non-null -- a renderbuffer without that should >> never exist. > > Is that true for i915? I've never understood i915.
Yes.
pgp8t1dDwC8yP.pgp
Description: PGP signature
_______________________________________________ mesa-dev mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/mesa-dev
