From: Michel Dänzer <[email protected]>
Signed-off-by: Michel Dänzer <[email protected]> --- lib/Target/R600/SIInstrInfo.cpp | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/lib/Target/R600/SIInstrInfo.cpp b/lib/Target/R600/SIInstrInfo.cpp index 4dfd26e..a8d573f 100644 --- a/lib/Target/R600/SIInstrInfo.cpp +++ b/lib/Target/R600/SIInstrInfo.cpp @@ -41,7 +41,33 @@ SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB, // never be necessary. assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC); - if (AMDGPU::VReg_64RegClass.contains(DestReg)) { + if (AMDGPU::VReg_256RegClass.contains(DestReg)) { + assert(AMDGPU::VReg_256RegClass.contains(SrcReg) || + AMDGPU::SReg_256RegClass.contains(SrcReg)); + BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), RI.getSubReg(DestReg, AMDGPU::sub0)) + .addReg(RI.getSubReg(SrcReg, AMDGPU::sub0), getKillRegState(KillSrc)) + .addReg(DestReg, RegState::Define | RegState::Implicit); + BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), RI.getSubReg(DestReg, AMDGPU::sub1)) + .addReg(RI.getSubReg(SrcReg, AMDGPU::sub1), getKillRegState(KillSrc)) + .addReg(DestReg, RegState::Define | RegState::Implicit); + BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), RI.getSubReg(DestReg, AMDGPU::sub2)) + .addReg(RI.getSubReg(SrcReg, AMDGPU::sub2), getKillRegState(KillSrc)) + .addReg(DestReg, RegState::Define | RegState::Implicit); + BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), RI.getSubReg(DestReg, AMDGPU::sub3)) + .addReg(RI.getSubReg(SrcReg, AMDGPU::sub3), getKillRegState(KillSrc)) + .addReg(DestReg, RegState::Define | RegState::Implicit); + BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), RI.getSubReg(DestReg, AMDGPU::sub4)) + .addReg(RI.getSubReg(SrcReg, AMDGPU::sub4), getKillRegState(KillSrc)) + .addReg(DestReg, RegState::Define | RegState::Implicit); + BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), RI.getSubReg(DestReg, AMDGPU::sub5)) + .addReg(RI.getSubReg(SrcReg, AMDGPU::sub5), getKillRegState(KillSrc)) + .addReg(DestReg, RegState::Define | RegState::Implicit); + BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), RI.getSubReg(DestReg, AMDGPU::sub6)) + .addReg(RI.getSubReg(SrcReg, AMDGPU::sub6), getKillRegState(KillSrc)) + .addReg(DestReg, RegState::Define | RegState::Implicit); + BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), RI.getSubReg(DestReg, AMDGPU::sub7)) + .addReg(RI.getSubReg(SrcReg, AMDGPU::sub7), getKillRegState(KillSrc)); + } else if (AMDGPU::VReg_64RegClass.contains(DestReg)) { assert(AMDGPU::VReg_64RegClass.contains(SrcReg) || AMDGPU::SReg_64RegClass.contains(SrcReg)); BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), RI.getSubReg(DestReg, AMDGPU::sub0)) -- 1.8.1.3 _______________________________________________ mesa-dev mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/mesa-dev
