On Wed, Oct 31, 2012 at 05:00:04PM +0100, Michel Dänzer wrote: > From: Michel Dänzer <[email protected]> > > Two SGPRs are used for VCC, so it's not possible to use these and VCC > together. >
Reviewed-by: Tom Stellard <[email protected]> > Signed-off-by: Michel Dänzer <[email protected]> > --- > lib/Target/AMDGPU/SIRegisterInfo.td | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/lib/Target/AMDGPU/SIRegisterInfo.td > b/lib/Target/AMDGPU/SIRegisterInfo.td > index a3d91ae..e52311a 100644 > --- a/lib/Target/AMDGPU/SIRegisterInfo.td > +++ b/lib/Target/AMDGPU/SIRegisterInfo.td > @@ -65,12 +65,12 @@ def SAMPLE_COVERAGE : SIReg <"SAMPLE_COVERAGE">; > def POS_FIXED_PT : SIReg <"POS_FIXED_PT">; > > // SGPR 32-bit registers > -foreach Index = 0-103 in { > +foreach Index = 0-101 in { > def SGPR#Index : SGPR_32 <Index, "SGPR"#Index>; > } > > def SGPR_32 : RegisterClass<"AMDGPU", [f32, i32], 32, > - (add (sequence "SGPR%u", 0, 103))>; > + (add (sequence "SGPR%u", 0, 101))>; > > // SGPR 64-bit registers > def SGPR_64 : RegisterTuples<[low, high], > -- > 1.7.10.4 > > _______________________________________________ > mesa-dev mailing list > [email protected] > http://lists.freedesktop.org/mailman/listinfo/mesa-dev _______________________________________________ mesa-dev mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/mesa-dev
