Paul Berry <[email protected]> writes: > On 31 August 2012 11:32, Eric Anholt <[email protected]> wrote: > >> The first cut at instruction compaction won't compact things that >> would change control flow jump distances, but we do need to still be >> able to walk the instruction stream, which involves jumping by 8 or 16 >> bytes between instructions. >> > > I'm not thrilled by the fact that after instruction compaction, p->store > still has type struct brw_instruction *, but the data it points to doesn't > always make sense as an array of struct brw_instruction. It seems like > there's a risk that we will later come along and add a p->store[...] > reference somewhere it doesn't belong, and get ourselves into trouble. But > I don't really have a better suggestion to offer.
Yeah, I didn't come up with something better either.
>> switch (insn->header.opcode) {
>> case BRW_OPCODE_BREAK:
>> - insn->bits3.break_cont.jip = br * (brw_find_next_block_end(p, ip)
>> - ip);
>> + insn->bits3.break_cont.jip =
>> + (brw_find_next_block_end(p, ip) - ip) / scale;
>> /* Gen7 UIP points to WHILE; Gen6 points just after it */
>> insn->bits3.break_cont.uip =
>> - br * (brw_find_loop_end(p, ip) - ip + (intel->gen == 6 ? 1 :
>> 0));
>> + (brw_find_loop_end(p, ip) - ip +
>> + (intel->gen == 6 ? 16 : 0)) / scale;
>>
>
> It looks from patch 7/8 like the WHILE instruction is never compacted, so I
> believe this is correct. However, if we ever decide to compact the WHILE
> instruction this will be wrong for gen6. Would it be possible to add an
> assertion here (or at the very least a comment) to alert us to the fact
> that this will need to be fixed when we get around to compacting WHILE?
The out-of-diff-context comment describing this function says that it's
just for adjusting break/cont (and HALT as well when we had that
around). I clarified that in the commit message.
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